I. Field of Invention
The present invention relates to the field of memory controllers and more particularly to a semiconductor chip for controlling the refreshing of a dynamic random access memory when a request for access to such memory by a remote peripheral device is present.
II. Description of the Prior Art
Dynamic random access memories (DRAM's) are composed of a plurality of memory cells in which each cell consists of a transistor network and an intrinsic capacitor. The transistors are used to charge the capacitor to store a "1" binary bit or to discharge the capacitor to store a "0" binary bit. Due to leakage, the memory cells must be refreshed periodically to keep the capacitors charged or discharged or else the integrity of the memory could not be relied upon. One common method of refreshing DRAM memories is by a row refresh approach (referred to as a RAS/-only Refresh). It is necessary to refresh each row of memory in the DRAM memory within a time period of two to four ms (milliseconds). In order to accomplish this, there are two basic approaches which could be used. One is to stop the processor from executing the current program and refresh all rows of memory. This is classified as a refresh operation. Another approach would be to interrupt the microprocessor every two to four ms and have it jump to a routine which would execute enough contiguous instructions to accomplish the memory refresh. Where there are other devices on the line with the memory system in which said devices may interrupt the normal processing operation or where there is a power down of the memory system, it is necessary that the DRAM memory be refreshed. Where a peripheral device has access to the DRAM memory at the same time that a contention refresh operation is required to occur, the processor will interrupt the memory access to allow the refresh operation to occur. Such an interruption degrades the potential system throughput by as much as ten percent.
It is therefore a principal object of this invention to provide an improved data processing system.
It is another object of this invention to increase the throughput of a data processing system.
It is a further object of this invention to provide a data processing system which allows a transparent refresh operation of a DRAM memory to occur at the time a remote peripheral device is requesting access to the DRAM memory.
It is another object of the invention to enable a multispeed microprocessor to interface with remote peripheral devices which operate at a different processing speed.